Technical Field
The present invention relates to semiconductor devices and processing, and more particularly to devices and methods that include source and drain regions that surround (wrap-around) an extremely thin semiconductor-on-insulator (ETSOI) channel area.
Description of the Related Art
In-situ doped epitaxy source and drain (S/D) regions followed by a diffusion anneal has been shown to form damage-free and lower resistance extension regions compared with implanted extension regions for field effect transistor (FET) devices. However, to ensure enough dopants are present in the S/D epitaxy, the S/D epitaxy region has to be large enough (e.g., thick enough to ensure sufficient dopants). Large (thick) S/D epitaxy undesirably increases the parasitic capacitance between a gate and the S/D epitaxy. For example, in raised S/D epitaxy regions, thick S/D materials are formed above the channel region resulting in high gate to S/D overlap capacitance. Another challenge with ETSOI is to form low contact resistance.